This invention relates to a microprogram control unit of a digital data processor and more particularly to a microinstruction access apparatus associated therewith.
It has become common place in the computer industry to develop data processors which include a control store (cs) comprising a plurality of microinstructions for controlling the operation of a register and arithmetic/logic unit (RALU). The control store is addressed based upon the contents of such microinstructions as well as other inputs depending upon the operation being executed in a data processor. Fetching the next microinstruction with its address conditionally based upon status information resulting from the execution of the current microinstruction is important in the data processor. If this was not done, then an additional microinstruction would be required because conditional addressing must be based upon status information generated by the execution of the previous microinstruction. Microprogram control and microinstruction design in the prior art are described in many references, one of which is "Digital System Design with LSI Bit-Slice Logic", Glenford J. Myers, John Wiley & Sons, Inc., 1980.
In addition, it is important that the fetching of the next microinstruction be performed in concurrence with the execution of the current microinstruction by the RALU. If this was not accomplished, the microinstruction execution time would be the sum of RALU execution time and the control store access time, and thus the total execution time would be significantly increased. Accordingly, it is desirable to fetch the next microinstruction with its address conditionally based upon status information resulting from the execution of the current microinstruction by the RALU in concurrence with the execution of the current microinstruction by the RALU. By providing such capability, the performance of the data processor is improved by neither requiring additional microinstructions nor slowing the microinstruction cycle time. Such a microprogram control store is shown and described in U.S. Pat. No. 4,587,611 to Gene M. Amdahl and Hsiao-Peng S. Lee and assigned to Amdahl Corporation of Sunnyvale, California. In Amdahl et al., a microprogram sequencing apparatus is disclosed having two or more control stores which enable a nonbranch address to fetch a first microinstruction from a first control store and a branch address to fetch a second microinstruction from a second control store. Since microinstructions from the branch and nonbranch addresses are concurrently available, no delay is encountered after the state of the branch condition is determined. However, additional hardware for the second control store is required to implement such microprogram sequencing apparatus.